Description of Related Art
The neuron MOS transistor (hereinbelow shortened to neuMOS) is a multi-input MOS transistor having a plurality of input gates, which calculates the weighting addition of all input signals and controls the ON OFF state of the transistor; such transistors have been the subject of a considerable amount of research in recent years as devices having a variety of functions.
It is possible to think of the neuMOS as dealing with multivalued signals within the device; it is capable of globally realizing a binary logical circuit using multivalues locally. When a logical circuit is designed using neuMOS, it is possible to greatly reduce the number of transistors in comparison with CMOS.
In the neuMOS, the MOSFET gate is made floating, and the structure is such that a plurality of input gate electrodes are coupled via a capacity with the floating gate. When a neuMOS logical circuit is actually constructed, a neuMOS inverter format having a CMOS structure is employed. The structure of the neuMOS inverter, and a circuit diagram thereof, are shown in FIG. 8.
If the coupling capacity of one input gate of a neuMOS inverter is fixed at Cc, then when the circuit inputs are connected to a number a of input gates, then it is possible to view the coupling capacity of the circuit inputs as a Cc. Now, if the input voltage in the circuit input Ii is represented by Vi, the coupling capacity of Ii is represented by ciCc (where ci is an integer), and the parasitic capacity of the neuMOS inverter is represented by C0, then the potential xcfx86 of the floating gate is represented by the following:                     [                  Arithmetic          ⁢                                    xe2x80x83                        ⁢                          xe2x80x83                                ⁢          Formula          ⁢                      xe2x80x83                    ⁢          1                ]                            xe2x80x83                                φ        =                                            ∑                              i                =                1                            n                        ⁢                                          c                i                            ⁢                              C                c                            ⁢                              V                i                                                          C            TOT                                              (        1        )                                                      C            TOT                    =                                    C              0                        +                          G              ·                              C                c                                                    ⁢                  
                ⁢                  G          =                                    ∑                              i                =                1                            n                        ⁢                          c              i                                                          (        2        )            
In the above formula, G represents the total number of input gates of the neuMOS inverter.
The output voltage of the neuMOS inverter changes based on the size relationship between the floating gate potential xcfx86 and the inversion threshold voltage Vth of the neuMOS inverter. The voltage VOUT of the output OUT of the neuMOS inverter can be expressed as the formula hereinbelow using formula (1).                     [                  Arithmetic          ⁢                                    xe2x80x83                        ⁢                          xe2x80x83                                ⁢          Formula          ⁢                      xe2x80x83                    ⁢          2                ]                            xe2x80x83                                          V          OUT                =                  {                                                                      V                  DD                                                                              (                                                                                                              ∑                                                      i                            =                            1                                                    n                                                ⁢                                                                              c                            i                                                    ⁢                                                      C                            c                                                    ⁢                                                      V                            i                                                                                                                      C                        TOT                                                               less than                                           V                      th                                                        )                                                                                                      V                  SS                                                                              (                                                                                                              ∑                                                      i                            =                            1                                                    n                                                ⁢                                                                              c                            i                                                    ⁢                                                      C                            c                                                    ⁢                                                      V                            i                                                                                                                      C                        TOT                                                               greater than                                           V                      th                                                        )                                                                                        (        3        )            
If Vth is set to xcex3VDD/2[V] (xcex3=Gxc2x7Cc/CTOT), and a variable Vi corresponding to 1 when Vi is VDD[V], and to 0 when Vi is CSS[V] is introduced, then it is possible to view the neuMOS inverter as an element which realizes the following threshold function from formula (3).                     [                  Arithmetic          ⁢                                    xe2x80x83                        ⁢                          xe2x80x83                                ⁢          Formula          ⁢                      xe2x80x83                    ⁢          3                ]                            xe2x80x83                                          f          ⁡                      (            x            )                          =                  {                                                                                                                1                                                                                      (                                                                                                            ∑                                                              i                                =                                1                                                            n                                                        ⁢                                                                                          c                                i                                                            ⁢                                                              x                                i                                                                                                               less than                                                       G                            2                                                                          )                                                                                                                        0                                                                                      (                                                                                                            ∑                                                              i                                =                                1                                                            n                                                        ⁢                                                                                          c                                i                                                            ⁢                                                              x                                i                                                                                                               greater than                                                       G                            2                                                                          )                                                                                            ⁢                                  
                                ⁢                x                            =                                                (                                                            x                      1                                        ,                    ⋯                    ⁢                                          xe2x80x83                                        ,                                          x                      n                                                        )                                ⁢                                  (                                                            i                      =                      1                                        ,                    ⋯                    ⁢                                          xe2x80x83                                        ,                    n                                    )                                                      ,                                          x                i                            ∈                              {                                  0                  ,                  1                                }                                                                        (        4        )            
Changing the way in which the neuMOS inverter is viewed, by causing the values (mCc/CTOT) VDD[V] (m=0, . . . , G) which may be taken by the floating gate potential xcfx86 to correspond to logical values m, the neuMOSinverter may be thought of as dealing with multivalued signals in a voltage mode within the device. In this way, G represents the total number of input gates of the neuMOS inverter, and simultaneously represents the number of multivalued levels which may be handled within the device.
Since an increase in G is linked to an increase in the multivalued levels handled in the device, it becomes possible to realize a variety of logical functions using one element, and it is possible to design logical circuits having even fewer elements. However, on the other hand, since CTOT is proportional to G, from formula (2), the value of the size Cc/CTOT) VDD of the change in potential which must be discriminated on the floating gate becomes even smaller. The minimum value of the change in potential which is to be discriminated on the floating gate is determined by the inversion threshold voltage Vth of the inverter, the size of the variation in the coupling capacity of the inputs, and the like. That is to say, the upper limit of G is determined by the precision of the device manufacturing process. The upper limit of G has an effect on the reliability of the circuit operation, so that this serves as an extremely strong constraint on the design of the neuMOS circuit.
As described above, the neuMOS inverter can be regarded as a threshold element which realizes formula (4). However, since the threshold function can not express a freely selected logical function, in order to realize a freely selected logical function using neuMOS, it is necessary to adopt a circuit structure in which a plurality of neuMOS inverters are combined.
A neuMOS circuit fulfilling the conditions stated below can be considered as one neuMOS circuit structure which realizes freely selected logical functions.
1. The circuit comprises a number n of circuit inputs and a number N from xcexd1 to xcexdN of neuMOS inverters, and the value of G of all the neuMOS inverters is constant.
2. All circuit inputs, VDD, and GND are inputted into all neuMOS inverters within the circuit. Furthermore, the coupling capacities with respect to the circuit input Ii are constant in all neuMOS inverters.
3. In addition to all circuit inputs, VDD, and GND, the outputs of the neuMOS inverters xcexd2, . . . , xcexdN are applied to neuMOS xcexd1 as inputs.
In the above circuit, signals are outputted from the circuit inputs through a maximum of 2 neuMOS inverters, so that this circuit will hereinafter be termed a 2-stage neuMOS circuit. The network structure of a 4-element 2-stage neuMOS circuit, in which the neuMOS inverters xcexd1, xcexd2, xcexd3, and xcexd4 are indicated by circles is shown in FIG. 9. In FIG. 9, a standard CMOS inverter is provided in order to amplify the output xcexd1.
The capacitive coupling of each neuMOS inverter is determined as given below.
ciCc: the capacitive coupling with respect to the input Ii of each neuMOS inverter.
ckDCc: the capacitive coupling with respect to the VDD input of xcexdk.
ckSCc: the capacitive coupling with respect to the VSS of xcexdk.
xcex1jCc: the capacitive coupling with respect to the xcexdj output of xcexd1.
At this time, the value of G of each neuMOS inverter is given by the formula below.                     [                  Arithmetic          ⁢                                    xe2x80x83                        ⁢                          xe2x80x83                                ⁢          Formula          ⁢                      xe2x80x83                    ⁢          4                ]                                                                    G              =                                                                    ∑                                          i                      =                      1                                        n                                    ⁢                                      c                    i                                                  +                                  c                  D                  1                                +                                  c                  S                  1                                +                                                      ∑                                          j                      =                      2                                        n                                    ⁢                                                            α                      j                                        ⁡                                          (                                              v                        1                                            )                                                                                                                                              =                                                                    ∑                                          i                      =                      1                                        n                                    ⁢                                      c                    i                                                  +                                  c                  D                  i                                +                                                      c                    S                    i                                    ⁡                                      (                                                                  v                        2                                            ,                      …                      ⁢                                              xe2x80x83                                            ,                                              v                        N                                                              )                                                                                          
Here, if it is assumed that c2D greater than  . . .  greater than cND, then applying formula (4), the 2-stage neuMOS circuit realizes the following function.                     [                  Arithmetic          ⁢                                    xe2x80x83                        ⁢                          xe2x80x83                                ⁢          Formula          ⁢                      xe2x80x83                    ⁢          5                ]                            xe2x80x83                                          f          ⁡                      (            x            )                          =                  {                                                                      {                                                                                    0                                                                                              (                                                                                                                    ∑                                                                  i                                  =                                  1                                                                n                                                            ⁢                                                                                                c                                  i                                                                ⁢                                                                  x                                  i                                                                                                                       less than                                                                                           G                                2                                                            -                                                              c                                D                                1                                                            -                                                                                                ∑                                                                      j                                    =                                    2                                                                    N                                                                ⁢                                                                  α                                  j                                                                                                                                              )                                                                                                                                    1                                                                                              (                                                                                                                    ∑                                                                  i                                  =                                  1                                                                n                                                            ⁢                                                                                                c                                  i                                                                ⁢                                                                  x                                  i                                                                                                                       greater than                                                                                           G                                2                                                            -                                                              c                                D                                1                                                            -                                                                                                ∑                                                                      j                                    =                                    2                                                                    N                                                                ⁢                                                                  α                                  j                                                                                                                                              )                                                                                                                                                                                          (                                                                                    ∑                                                  i                          =                          1                                                n                                            ⁢                                                                        c                          i                                                ⁢                                                  x                          i                                                                                       less than                                                                   G                        2                                            -                                              c                        D                        2                                                                              )                                                                                                      {                                                                                    0                                                                                              (                                                                                                                    ∑                                                                  i                                  =                                  1                                                                n                                                            ⁢                                                                                                c                                  i                                                                ⁢                                                                  x                                  i                                                                                                                       less than                                                                                           G                                2                                                            -                                                              c                                D                                1                                                            -                                                                                                ∑                                                                      j                                    =                                    k                                                                    N                                                                ⁢                                                                  α                                  j                                                                                                                                              )                                                                                                                                    1                                                                                              (                                                                                                                    ∑                                                                  i                                  =                                  1                                                                n                                                            ⁢                                                                                                c                                  i                                                                ⁢                                                                  x                                  i                                                                                                                       greater than                                                                                           G                                2                                                            -                                                              c                                D                                1                                                            -                                                                                                ∑                                                                      j                                    =                                    k                                                                    N                                                                ⁢                                                                  α                                  j                                                                                                                                              )                                                                                                                                                                                          (                                                                                    G                        2                                            -                                              c                        D                                                  k                          -                          1                                                                                       less than                                                                   ∑                                                  i                          =                          1                                                n                                            ⁢                                                                        c                          i                                                ⁢                                                  x                          i                                                                                       less than                                                                   G                        2                                            -                                              c                        D                        k                                                                              )                                                                                                      (                                                            k                      =                      3                                        ,                    …                    ⁢                                          xe2x80x83                                        ,                    N                                    )                                                                                                      {                                                                                    0                                                                                              (                                                                                                                    ∑                                                                  i                                  =                                  1                                                                n                                                            ⁢                                                                                                c                                  i                                                                ⁢                                                                  x                                  i                                                                                                                       less than                                                                                           G                                2                                                            -                                                              c                                D                                1                                                                                                              )                                                                                                                                    1                                                                                              (                                                                                                                    ∑                                                                  i                                  =                                  1                                                                n                                                            ⁢                                                                                                c                                  i                                                                ⁢                                                                  x                                  i                                                                                                                       greater than                                                                                           G                                2                                                            -                                                              c                                D                                1                                                                                                              )                                                                                                                                                                                          (                                                                                    G                        2                                            -                                              c                        D                        N                                                               less than                                                                   ∑                                                  i                          =                          1                                                n                                            ⁢                                                                        c                          i                                                ⁢                                                  x                          i                                                                                                      )                                                                                        (        5        )            
Formula (5) expresses a multiple threshold function having a plurality of threshold values, in which the output changes each time the value of the weighting addition exceeds a threshold value. If the multiple threshold function does not constrain the number of threshold values, it is possible to express freely selected logical functions, so that the 2-stage neuMOS circuit is capable of realizing freely selected logical functions. Furthermore, considering this from the other direction, if the multiple threshold function expression of a logical function is known, then the design of a 2-stage neuMOS circuit which realizes that function is a simple matter from formula (5).
However, a plurality of multiple threshold function expressions of a logical function exist, so that it is necessary to find, from among the 2-stage neuMOS circuits corresponding to the multiple threshold function expressions, that circuit which is best suited to actual implementation.
A (7,3) parallel counter circuit diagram is shown in FIG. 10 as an example of a 2-stage neuMOS circuit. The (7,3) parallel counter is a circuit which, in response to 7 inputted signals, outputs a 3-place signal expressing in binary numbers the number of input signals having a value of 1.
With respect to the layout of this circuit, the 2-stage neuMOS circuit may have a systematic layout as in the circuit diagram. As an example, the layout of the circuit diagram of the two-stage neuMOS circuit of FIG. 11(a) is shown in FIG. 11(b). From the layout diagram, when the design rules are determined, the surface area A of the 2-stage neuMOS circuit may be approximated as shown in formula (6) asarectangular surface area in which the length in the vertical direction is a linear function of G, and the length in the horizontal direction is a linear function of the number N of neuMOS inverters.
xe2x80x83A=(a1N+a2)(b1G+b2)xe2x80x83xe2x80x83(6)
In the above formula, a1, a2, b1, and b2 are constants which are determined by the design rules.
From the above results, the present inventors proposed a method for realizing an appropriate logical function using integer programming and for designing a 2-stage neuMOS circuit having the minimum surface area. The results of designs conducted with respect to full 3-input functions using this method are shown in Tables 1-3. The results in Tables 1-3 presuppose the circuit structure shown in FIG. 9, in which a CMOS inverter is provided in order to amplify the output of the final stage neuMOS inverter of the two-stage neuMOS circuit, and the output of the CMOS inverter serves as the final circuit output.
The circuit structure of a 2-stage neuMOS circuit is fixed, so that in cases in which the value of G exceeds the upper limit of G (Glim) which is determined by the precision of the device manufacturing process described above, the function cannot be realized.
In light of the above circumstances, the present invention has as an object thereof to provide a logical operational circuit which serves to realize, using neuMOS, logical functions which were previously impossible to realize using 2-stage neuMOS circuits as a result of Glim constraints.
Furthermore, the present invention has as an object thereof to provide a logical operational circuit such that when the logical operational circuit is realized, the surface area when mounted is reduced in size, and which permits large scale integration.
Furthermore, the present invention has as an object thereof to provide an LSI logical operational circuit which is easy to manufacture.
The logical operational circuit of the present invention comprises 3 or more neuMOS inverters having a CMOS structure which have a floating gate and 1 or 2 or more input gates capacitively coupled with this floating gate, wherein the output of the third neuMOS inverter is connected via a capacity with the floating gate of the second neuMOS inverter, and the output of the second neuMOS inverter is connected via a capacity with the floating gate of the first neuMOS inverter, and the respective input signals are connected to at least 1 or more input gates of the neuMOS inverters in the circuit, predetermined logical operations are conducted with respect to the plurality of input signals, and the results thereof form the output of the first neuMOS inverter.
Furthermore, the logical operational circuit of the present invention comprises 3 or more neuMOS inverters having a CMOS structure which have a floating gate and 1 or 2 or more input gates capacitively coupled with the floating gate, wherein the output of the third neuMOS inverter and the output of the second neuMOS inverter are connected via a capacity with the floating gate of the first neuMOS inverter, and the various input signals are connected with at least 1 or more of the input gates of the neuMOS inverters in the circuit, predetermined logical operations are conducted with respect to the plurality of input signals, and the results thereof form the output of the first neuMOS inverter.
In the present invention, at least one of the high voltage power source and the low voltage power source is capacitively coupled with at least one of the floating gates of the first, second, and third neuMOS inverters.